The disclosure relates generally to efficient interruption routing for a multithreaded processor, and more specifically, to a modified priority routing of input/output (I/O) interruption that facilitates a host or an enabled core to handle threads in waiting.
In general, processor speed has increased over the past decades, while there has not been a proportional increase in memory access speed. In turn, the faster a processor cycle time in a computing system, the more pronounced a delay is when waiting for data from memory. The effects of such delays may be mitigated by multithreading within a processor of the computing system, which allows various cores of the processor to be shared by a plurality of instruction streams known as threads. For example, during latency in a first thread being processed by a core, a second thread can utilize resources of that core.
Yet, to take advantage of the latency, the core must receive an I/O interruption. Current management practices of I/O interruptions require that an enabled host (e.g. a hypervisor) receive the interruption for processing at a higher priority than any enabled guest of the core. Thus, the host itself must then perform the initial processing of a guest's interruption, and then dispatch an enabled thread, possibly the same thread that had been operating on the core, to complete the I/O interruption processing. Unfortunately, these current management practices of I/O interruptions by a host while the one of the current guest threads are enabled for the same I/O interruption cause processing latency.